A liquid crystal display apparatus includes a timing controller and a panel driving unit in order to drive a panel that displays image data. The timing controller processes the image data and generates a timing control signal, and the panel driving unit includes a gate driver and a source driver and drives the panel based on the image data and the timing control signal transmitted from the timing controller.
The source driver has a plurality of power output ports for driving horizontal lines of the liquid crystal display apparatus and outputs a voltage at a specific time at which the horizontal lines are driven, thereby generating power noise therein. Since the conventional liquid crystal display apparatus independently includes a clock line required for detecting image data and an image data transmission speed between the timing controller and the source driver is not fast, the conventional liquid crystal display apparatus performs a normal operation even though power noise exists.
In a recent liquid crystal display apparatus, as a high refresh rate (reproduction frequency) with a large area is required, high speed image data transmission is required between a timing controller and a source driver, and a CEDS (CLOCK Embedded Differential Signaling) scheme, in which a clock signal is embedded in a data signal, has been employed.
In such a CEDS scheme, since an independent clock signal is not input from an exterior and the source driver generates a clock signal by itself based on input CED (CLOCK Embedded Data), there is a problem that the CEDS scheme is affected by power noise.
That is, when power noise occurs, since the source driver erroneously recognizes a clock signal and a data signal from the received CED and a lock signal LOCK indicating an operation state of the source driver falls to a Low level, the timing controller enters a CLOCK training stage in which a clock is synchronized, resulting in a problem that an error occurs in image data detection.